Technical Field
The present invention relates to a package substrate for chip/chips package, especially relates to a package substrate having molding compound wrapped four lateral sides and bottom side to stiffen the high density package substrate.
Description of Related Art
FIG. 1 Shows a Prior Art.
FIG. 1 shows a prior art package substrate for chip package. US20120146209A1 disclosed a chip package which has a through-holed interposer 21, a redistribution-layer 213 disposed on a top side of the interposer 21. A molding layer 22 is formed to embed the through-holed interposer 21. The molding layer 22 has an exposed first surface 22a and a second surface 22b. A built-up structure 24 is formed on the second surface 22b of the molding layer 22. The built-up structure 24 comprises a dielectric layer 240 and a wiring layer 241, such that the conductive vias 242 are formed in the dielectric layer 240 for electrically connecting the wiring layer 241 to the conductive through metal 210. A solder mask layer 25 is formed on the outermost dielectric layer 240 to expose conductive pads 243. The through-holed interposer 21 is made of glass or ceramic such as Al2O3 and AlN, wherein the ceramic has a CTE of about 3 ppm/° C. that is close to silicon. A chip 27 is flip-chip electrically connected to the electrode pads 211 of the redistribution-layer 213 through a plurality of solder bumps 271, an underfill 270 is used to fill the space between the electrode pads 211 and the chip 27, and a plurality of solder balls 26 are mounted on the conductive pads 243 for the package to electrically coupled to an outside print circuit board (not shown).
The prior art package substrate is mainly stiffened by the glass/ceramic interposer 21. However, semiconductor package technology moves faster and faster, a thinner thickness package substrate without having a glass/ceramic interposer is developed, a different stiffening structure has to be conceived for a high density package substrate used for chip or chips package.